The present invention relates generally to integrated circuits and, more particularly, to generating multi-phase, non-overlapping clock signals used in integrated circuits.
Many digital signal processing circuits require synchronized clock signals for synchronizing the operations of internal circuits. Multi-phase clock signals are generally used as synchronized clock signals in circuits including cyclic analog-to-digital converters (ADCs). Multi-phase clock signals are generated by dividing the frequency of a reference clock signal. In addition to synchronization, multi-phase clock signals must meet other specific requirements of the digital signal processing circuits. One such requirement is the generation of non-overlapping clock signals. Non-overlapping clock signals are clock signals having active periods that do not overlap. FIG. 1 shows a timing diagram of two non-overlapping clock signals, Ph1 and Ph2 in which the active periods Ph1 and Ph2 do not overlap.
FIG. 2 is a schematic diagram of a conventional circuit 200 for generating multi-phase, non-overlapping clock signals. The circuit 200 generates a set of four non-overlapping clock signals that are phase-shifted from each other and includes a shift register 202 that receives an input clock signal 204 and divides the frequency of the input clock signal 204 to generate four phase-shifted clock signals QA, QB, QC and QD. The number of phase-shifted clock signals corresponds to the number of non-overlapping clock signals required to be generated by the circuit 200. The phase-shifted clock signals QA, QB, QC and QD are provided to corresponding circuit modules 206a, 206b, 206c and 206d (collectively referred to as circuit modules 206). Each circuit module 206 includes a NOT gate connected to a NOR gate. As shown, the circuit module 206a includes NOT gate 208a connected to NOR gate 210a. The NOT gate 208a receives the clock signal QA, inverts it, and provides the inverted clock signal to an input of the NOR gate 210a. The NOR gate 210a also receives a feedback signal FB4 and generates a first clock signal Ph1. Similarly, the circuit modules 206b-206d generate second, third and fourth clock signals, Ph2, Ph3 and Ph4. The set of clock signals Ph1-Ph4 are delayed using corresponding delay circuits 212a-212d, which generally comprise strings of buffers. The delay circuits 212a-212d introduce a predetermined time delay Td and generate corresponding feedback signals FB1, FB2, FB3, and FB4. The feedback signals FB2-FB4 are provided to the circuit modules 206a-206d in a cyclic order, i.e., the feedback signal generated using one clock signal is provided to a circuit module generating the next clock signal. Thus, feedback signals FB1, FB2, FB3 and FB4 are provided to the circuit modules 206b, 206c, 206d and 206a, respectively. As mentioned earlier, the feedback signals FB2-FB4 are provided as inputs to the respective NOR gates 210b, 210c, 210d and 210a to ensure that the clock signals Ph1-Ph4 have non-overlapping active periods and adjacent clock signals (i.e., Ph1 and Ph2, Ph2 and Ph3, Ph3 and Ph4, and Ph4 and Ph1) are separated by the predetermined time Td. As shown in FIG. 1, the active periods of the clock signals Ph1 and Ph2 are separated by the predetermined time Td.
The conventional circuit 200 introduces significant area overhead when transferred to an integrated circuit because it uses a separate circuit arrangement for generating each non-overlapping clock signal. For example, the clock signal Ph1 is generated using the circuit module 206a and the delay circuit 212a. The overhead increases proportionally with the number of non-overlapping clock signals generated. Also, generation of each clock signal using a separate delay circuit introduces small variations in the delay time Td. These variations lead to time mismatches between the non-overlapping clock signals and lower the performance of a cyclic ADC or any other circuit that uses such clock signals.
Therefore, there is a need for a circuit that generates multi-phase, non-overlapping clock signals and does not significantly increase area overhead and that overcomes the above-mentioned limitations.